As is known, memory devices are typically organized as an array of memory cells in which word lines connect gate terminals of the cells placed on the same line and bit lines connect drain terminals of the cells placed on the same column. Individual lines of the memory array are then addressed by means of a line decoder receiving at the input a coded address.
A line decoder may be schematically represented by means of a plurality of inverters, one inverter for each line. Each inverter is made up of a "pull-up" transistor and a "pull-down" transistor and is controlled by a combinatorial circuit receiving at the input the coded addresses. The combinatorial circuit, in turn, causes the output of only one of the inverters, in particular the one that drives the selected address line, to a high logic value.
In order to guarantee the correct operation of the line decoder during both reading and programming phases of the memory cells, a PMOS reaction transistor is typically provided between the output of the line decoder and the input of each inverter. When turned on, the PMOS reaction transistor allows the input of the inverter to be brought to a voltage equal to the supply voltage, thus guaranteeing that the pull-up transistor of the inverter is completely turned off and the output voltage of the inverter is zero. Upstream of each inverter there is also a pass transistor, the purpose of which is to separate the low voltage part (predecoding) from the high voltage part (real decoding) so as to avoid malfunctions due to the possible direct biasing of drain/bulk junctions in the P-channel transistor located upstream.
At present there is a need to guarantee the operation of integrated devices at low supply voltage, especially to satisfy the typical low power consumption requirements of portable devices, for example, cellular phones.
On the other hand, the reduction of the supply voltage gives rise to a series of problems. In particular, reading memory cells becomes particularly delicate, as reading errors linked with the distribution of cell threshold voltages may arise. In fact, the reading voltage supplied to the gate terminals of the cells to be read is generally equal to the supply voltage, and consequently, all the erased cells having a threshold voltage close to the supply voltage will not conduct current during reading, or alternatively, will conduct very low current. Consequently, those cells will be erroneously read as written cells.
To solve this problem, a solution has been proposed that is based on the principle of raising the reading voltage. That is, supplying the gate terminal of the cell to be read with a voltage higher than the supply voltage that is generated by means of a special stage known as a "boost stage." In this way, even those erased cells having a threshold voltage very close to the supply voltage can be made conductive and be correctly read.
Currently, there are different solutions based on this principle. For example, continuous boost, global pulsed boost, local pulsed boost limited to one p-channel channel threshold, and local pulsed boost limited to two p-channel thresholds. Each of these aforementioned will be discussed in more detail below.
In the "continuous boost" solution, a boost condenser is gradually charged up to a voltage greater than the supply voltage by means of a train of pulses. The boost condenser then maintains a common memory line (boost line) at the desired overvoltage. This solution offers the advantage that the boost condenser does not need to be of a high capacity, since the overvoltage is produced by means of a series of small increases and so the area occupied by the condenser is relatively small. For this same reason, however, the time needed for the initial charging of the condenser is relatively long, so the memory devices that use this solution have a long access time after turning on or when reactivating after stand-by condition.
To overcome this problem, it is possible to use a second boost stage which keeps the boost condenser charged during stand-by condition, but consequently, the current consumption during the stand-by condition increases.
In the "global pulsed boost" solution, a boost condenser having a very high capacity is used and it is charged by means of a single pulse only when reading of a memory cell is requested. For example, when the addresses switch (during a reading step ) or when the chip enable signal switches to the active status, the high capacity boost condenser is charged. This solves the problems linked with the high access time when turning on or when returning from stand-by condition and with increased current consumption during stand-by condition. However, other problems arise, such as, the large area occupied by the high capacity boost condenser and the necessary driving circuits, and the timing of the condenser charging step.
The solutions with "local pulsed boost limited to one p-channel threshold" and "local pulsed boost limited to two p-channel thresholds" take advantage of the continuous boost and of the global pulsed boost, as they allow the reading voltage to be raised only when it is really necessary. These solutions are described in EP-A-0 814 481 and in European Patent Application No. 97830739.5 filed on Dec. 31, 1997.
However, these solutions are also not without problems. For example, in the case of the load pulsed boost limited to one-p-channel threshold solution, the boost voltage that can be generated must not exceed an upper limit equal to the supply voltage plus one p-channel threshold to guarantee turning on only the driving inverter of the line to be addressed and turning off of the driving inverters of the other lines in the same sector. Similarly, the boost voltage generated must not exceed the supply voltage plus two p-channel thresholds in the case of the local pulsed boost limited to two p-channel threshold solution. These limits on the boost voltage are quite incompatible with the demands of future generations of memory devices operating with supply voltages close to 1 V.